ARM Cortex-A35 User Manual

C10.8 Performance Monitors Common Event Identification Register 1, EL0
The PMCEID1_EL0 characteristics are:
Purpose
Defines which common architectural and common microarchitectural feature events are
implemented.
Usage constraints
This register is accessible as follows:
EL0 EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
Config RO RO RO RO RO
This register is accessible at EL0 when PMUSERENR_EL0.EN is set to 1.
Configurations
The PMCEID1_EL0 is architecturally mapped to:
• The AArch32 register PMCEID1. See C10.4 Performance Monitors Common Event
Identification Register 1 on page C10-699.
• The external register PMCEID1_EL0.
Attributes
PMCEID1_EL0 is a 32-bit register.
31
0
RES0
17 16
CE [48:32]
Figure C10-6 PMCEID1 bit assignments
[31:17]
RES0.
CE[48:32], [16:0]
Common architectural and microarchitectural feature events that can be counted by the PMU
event counters.
For each bit described in The following table, the event is implemented if the bit is set to 1, or
not implemented if the bit is set to 0.
Table C10-6 PMU common events
Bit Event number Event mnemonic Description
[16]
0x30
L2I_TLB
Attributable Level 2 instruction TLB access.
0
This event is not implemented.
[15]
0x2F
L2D_TLB Attributable Level 2 data or unified TLB access.
0
This event is not implemented.
[14]
0x2E
L2I_TLB_REFILL Attributable Level 2 instruction TLB refill.
0
This event is not implemented.
C10 PMU registers
C10.8 Performance Monitors Common Event Identification Register 1, EL0
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English