Table C10-6 PMU common events (continued)
Bit Event number Event mnemonic Description
[13]
0x2D
L2D_TLB_REFIL Attributable Level 2 data or unified TLB refill.
0
This event is not implemented.
[12]
0x2C
L3D_CACHE_WB Attributable Level 3 data or unified cache write-back.
0
This event is not implemented.
[11]
0x2B
L3D_CACHE Attributable Level 3 data or unified cache access.
0
This event is not implemented.
[10]
0x2A
L3D_CACHE_REFILL Attributable Level 3 data or unified cache refill.
0
This event is not implemented.
[9]
0x29
L3D_CACHE_ALLOCATE Attributable Level 3 data or unified cache allocation without refill.
0
This event is not implemented.
[8]
0x28
L2I_CACHE_REFILL Attributable Level 2 instruction cache refill.
0
This event is not implemented.
[7]
0x27
L2I_CACHE Attributable Level 2 instruction cache access.
0
This event is not implemented.
[6]
0x26
L1I_TLB Level 1 instruction TLB access.
0
This event is not implemented.
[5]
0x25
L1D_TLB Level 1 data or unified TLB access.
0
This event is not implemented.
[4]
0x24
STALL_BACKEND No operation issued due to backend.
0
This event is not implemented.
[3]
0x23
STALL_FRONTEND No operation issued due to the frontend.
0
This event is not implemented.
[2]
0x22
BR_MIS_PRED_RETIRED Instruction architecturally executed, mispredicted branch.
0
This event is not implemented.
[1]
0x21
BR_RETIRED Instruction architecturally executed, branch.
0
This event is not implemented.
[0]
0x20
L2D_CACHE_ALLOCATE Level 2 data cache allocation without refill.
0
This event is not implemented.
C10 PMU registers
C10.8 Performance Monitors Common Event Identification Register 1, EL0
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
C10-712
Non-Confidential
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