ARM Cortex-A35

To access the PMCEID1_EL0:
MRS <Xt>, PMCEID1_EL0; Read Performance Monitor Common Event Identification Register 0
The PMCEID1_EL0 can be accessed through the external debug interface, offset 0xE24.
C10 PMU registers
C10.8 Performance Monitors Common Event Identification Register 1, EL0
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C10-713
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