ARM Cortex-A35 User Manual

B1.43 CPU Extended Control Register
The CPUECTLR characteristics are:
Purpose
Provides additional IMPLEMENTATION DEFINED configuration and control options for the processor.
Usage constraints
This register is accessible as follows:
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - RW RW RW RW RW
The CPUECTLR can be written dynamically.
Configurations
The CPUECTLR is mapped to the AArch64 CPUECTLR_EL1 register. See B2.37 CPU
Extended Control Register, EL1 on page B2-416.
Attributes
CPUECTLR is a 64-bit register.
7
6 5 3 2
RES0
063
SMPEN
FPRETCTL
CPURETCTL
Figure B1-7 CPUECTLR bit assignments
[63:7]
Reserved, RES0.
SMPEN, [6]
Enable hardware management of data coherency with other cores in the cluster. The possible
values are:
0 Disables data coherency with other cores in the cluster. This is the reset value.
1 Enables data coherency with other cores in the cluster.
Set the SMPEN bit before enabling the caches, even if there is only one core in the system.
FPRETCTL, [5:3]
Advanced SIMD and floating-point retention control. The possible values are:
0b000 Disable the retention circuit. This is the reset value.
0b001 2 Architectural Timer ticks are required before retention entry.
0b010 8 Architectural Timer ticks are required before retention entry.
0b011 32 Architectural Timer ticks are required before retention entry.
0b100 64 Architectural Timer ticks are required before retention entry.
0b101 128 Architectural Timer ticks are required before retention entry.
0b110 256 Architectural Timer ticks are required before retention entry.
B1 AArch32 system registers
B1.43 CPU Extended Control Register
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B1-212
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English