0 Enable dynamic stride adjustment. This is the reset value.
1 Disable dynamic stride adjustment.
DODMBS, [10]
Disable optimized Data Memory Barrier behavior. The possible values are:
0 Enable optimized Data Memory Barrier behavior. This is the reset value.
1 Disable optimized Data Memory Barrier behavior.
[9:7]
Reserved, RES0.
L1DEIEN, [6]
L1 D-cache data RAM error injection enable. The possible values are;
0 Normal behavior, errors are not injected. This is the reset value.
1 Double-bit errors are injected on all writes to the L1 D-cache data RAMs for the
first word of each 32-byte region.
[5:0]
Reserved, RES0.
To access the CPUACTLR:
MRRC p15, 0, <Rt>, <Rt2>, c15; Read CPU Auxiliary Control Register
MCRR p15, 0, <Rt>, <Rt2>, c15; Write CPU Auxiliary Control Register
Register access is encoded as follows:
Table B1-36 CPUACTLR access encoding
coproc opc1 CRm
1111 0000 1111
B1 AArch32 system registers
B1.42 CPU Auxiliary Control Register
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-211
Non-Confidential
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