ARM Cortex-A35 User Manual

B2.41 Exception Syndrome Register, EL1
The ESR_EL1 characteristics are:
Purpose
Holds syndrome information for an exception taken to EL1.
Usage constraints
This register is accessible as follows:
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- RW RW RW RW RW
Configurations
ESR_EL1 is architecturally mapped to AArch32 register DFSR (NS). See B1.49 Data Fault
Status Register on page B1-223.
Attributes
ESR_EL1 is a 32-bit register.
31
0
ISS
IL
EC
25 2426
ISS Valid
23
Figure B2-16 ESR_EL1 bit assignments
EC, [31:26]
Exception Class. Indicates the reason for the exception that this register holds information
about.
IL, [25]
Instruction Length for synchronous exceptions. The possible values are:
0 16-bit.
1 32-bit.
This field is 1 for the SError interrupt, instruction aborts, misaligned PC, Stack pointer
misalignment, data aborts for which the ISV bit is 0, exceptions caused by an illegal instruction
set state, and exceptions using the 0x00 Exception Class.
ISS Valid, [24]
Syndrome valid. The possible values are:
0 ISS not valid, ISS is RES0.
1 ISS valid.
ISS, [23:0]
Syndrome information.
When the EC field is 0x2F, indicating an SError interrupt has occurred, the ISS field contents are
IMPLEMENTATION DEFINED.
B2 AArch64 system registers
B2.41 Exception Syndrome Register, EL1
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English