ARM Cortex-A35 User Manual

Table B2-32 ISS field contents for the Cortex-A35 processor
ISS[23:22] ISS[1:0] Description
0b00 0b00
DECERR on external access
0b00 0b01
Double-bit error detected on dirty line in L2 cache
0b00 0b10
SLVERR on external access
0b01 0b00
nSEI, or nVSEI in a guest OS, asserted
0b01 0b01
nREI asserted
To access the ESR_EL1:
MRS <Xt>, ESR_EL1 ; Read EL1 Exception Syndrome Register
MSR ESR_EL1, <Xt> ; Write EL1 Exception Syndrome Register
Register access is encoded as follows:
Table B2-33 ESR_EL1 access encoding
op0 op1 CRn CRm op2
11 000 0101 0010 000
B2 AArch64 system registers
B2.41 Exception Syndrome Register, EL1
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English