ARM Cortex-A35 User Manual

B1.87 Instruction Fault Status Register
The IFSR characteristics are:
Purpose
Holds status information about the last instruction fault.
Usage constraints
This register is accessible as follows:
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - RW RW RW RW RW
Configurations
IFSR (NS) is architecturally mapped to AArch64 register IFSR32_EL2. See B2.69 Instruction
Fault Status Register, EL2 on page B2-479.
If EL3 is using AArch32, there are separate Secure and Non-secure instances of this register.
Attributes
IFSR is a 32-bit register.
There are two formats for this register. The current translation table format determines which format of
the register is used.
B1 AArch32 system registers
B1.87 Instruction Fault Status Register
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B1-294
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English