B1.104 Secure Configuration Register
The SCR characteristics are:
Purpose
Defines the configuration of the current security state. It specifies:
• The security state of the processor, Secure or Non-secure.
• What state the processor branches to, if an IRQ, FIQ or external abort occurs.
• Whether the CPSR.F and CPSR.A bits can be modified when SCR.NS = 1.
Usage constraints
This register is accessible as follows:
EL0
NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - - RW - RW RW
Any read or write to SCR in Secure EL1 state in AArch32 is trapped as an exception to EL3.
Configurations
The SCR is a Restricted access register that exists only in the Secure state.
The SCR is mapped to the AArch64 SCR_EL3 register. See B2.92 System Control Register, EL3
on page B2-532.
Attributes
SCR is a 32-bit register.
31 10 9 8 7 6 4 3 2 1 0
RES0
SIF
HCE
FIQ
IRQ
NS
TWI
TWE
11121314
SCD
5
nET
EA
FW
AW
RES0
Figure B1-57 SCR bit assignments
[31:14]
Reserved, RES0.
TWE, [13]
Trap WFE instructions. The possible values are:
0 WFE instructions are not trapped. This is the reset value.
1 WFE instructions executed in any mode other than Monitor mode are trapped to Monitor mode
as UNDEFINED if the instruction would otherwise cause suspension of execution, that is if:
• The event register is not set.
• There is not a pending WFE wakeup event.
• The instruction does not cause another exception.
B1 AArch32 system registers
B1.104 Secure Configuration Register
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-328
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