ARM Cortex-A35 User Manual

B2.92 System Control Register, EL3
The SCTLR_EL3 characteristics are:
Purpose
Provides top level control of the system, including its memory system at EL3.
SCTLR_EL3 is part of the Virtual memory control registers functional group.
Usage constraints
This register is accessible as follows:
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - - - RW RW
Configurations
SCTLR_EL3 is mapped to AArch32 register SCTLR(S). See B1.105 System Control Register
on page B1-331.
Attributes
SCTLR_EL3 is a 32-bit register.
31
0
RES0
SA
WXNEE
I MAC
4 3 22526 24 1920 18 113 12 1130 29 28 27
RES1 RES0
23 22 21
RES0RES1
RES0
17 16 15
RES0
RES1
RES0RES1
10 9 8 7 6 5
RES1
RES0 RES1
Figure B2-63 SCTLR_EL3 bit assignments
[31:30]
Reserved, RES0.
[29:28]
Reserved, RES1.
[27:26]
Reserved, RES0.
EE, [25]
Exception endianness. This bit controls the endianness for:
• Explicit data accesses at EL3.
• Stage 1 translation table walks at EL3.
The possible values are:
0 Little endian. This is the reset value.
1 Big endian.
[24]
Reserved, RES0.
[23:22]
Reserved, RES1.
[21:20]
Reserved, RES0.
B2 AArch64 system registers
B2.92 System Control Register, EL3
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reserved.
B2-532
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English