ARM Cortex-A35 User Manual

B1.60 Hyp Architectural Feature Trap Register
The HCPTR characteristics are:
Purpose
Controls trapping to Hyp mode of Non-secure access, at EL1 or lower, to coprocessors other
than CP14 and CP15 and to floating-point and Advanced SIMD functionality. Also controls
access from Hyp mode to this functionality.
Usage constraints
This register is accessible as follows:
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - - - RW RW -
If a bit in the NSACR prohibits a Non-secure access, then the corresponding bit in the HCPTR
behaves as RAO/WI for Non-secure accesses. See the bit description for TASE.
Configurations
HCPTR is architecturally mapped to AArch64 register CPTR_EL2. See B2.32 Architectural
Feature Trap Register, EL2 on page B2-404.
Attributes
HCPTR is a 32-bit register.
RES1
31 30 21 20 19 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
RES0
TCPAC
RES0
TTA TASE
TCP11
TCP10
RES1
RES0
Figure B1-16 HCPTR bit assignments
TCPAC, [31]
Trap CPACR accesses. The possible values of this bit are:
0 Has no effect on CPACR accesses.
1 Trap valid Non-secure EL1 CPACR accesses to Hyp mode.
When this bit is set to 1, any valid Non-secure EL1 access to the CPACR is trapped to Hyp
mode.
Resets to 0.
[30:21]
Reserved, RES0.
TTA, [20]
Trap Trace Access.
Not implemented. RES0.
[19:16]
Reserved, RES0.
B1 AArch32 system registers
B1.60 Hyp Architectural Feature Trap Register
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-237
Non-Confidential

ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English