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ARM Cortex-A35 User Manual

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B1.68 Hyp Syndrome Register
The HSR characteristics are:
Purpose
Holds syndrome information for an exception taken to Hyp mode.
Usage constraints
This register is accessible as follows:
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - - - RW RW -
Configurations
HSR is architecturally mapped to AArch64 register ESR_EL2. See B2.42 Exception Syndrome
Register, EL2 on page B2-425.
This register is accessible only at EL2 or EL3.
Attributes
HSR is a 32-bit register.
ISS
31 26 25 24 0
EC
IL
Figure B1-24 HSR bit assignments
EC, [31:26]
Exception class. The exception class for the exception that is taken in Hyp mode. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile for more information.
IL, [25]
Instruction length. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A
architecture profile for more information.
ISS, [24:0]
Instruction specific syndrome. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-
A architecture profile for more information. The interpretation of this field depends on the value
of the EC field. See B1.52 Encoding of ISS[24:20] when HSR[31:30] is 0b00 on page B1-228.
B1 AArch32 system registers
B1.68 Hyp Syndrome Register
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-258
Non-Confidential

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ARM Cortex-A35 Specifications

General IconGeneral
BrandARM
ModelCortex-A35
CategoryComputer Hardware
LanguageEnglish

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