Load/store exclusive and load-acquire/store-release instructions have this alignment check
regardless of the value of the A bit.
If this register is at the highest exception level implemented, field resets to 0. Otherwise, its
reset value is UNKNOWN.
M, [0]
MMU enable. This is a global enable bit for the EL2 stage 1 MMU:
0 EL2 stage 1 MMU disabled.
1 EL2 stage 1 MMU enabled.
If this register is at the highest exception level implemented, field resets to 0. Otherwise, its
reset value is UNKNOWN.
To access the HSCTLR:
MRC p15,4,<Rt>,c1,c0,0 ; Read HSCTLR into Rt
MCR p15,4,<Rt>,c1,c0,0 ; Write Rt to HSCTLR
Register access is encoded as follows:
Table B1-52 HSCTLR access encoding
coproc opc1 CRn CRm opc2
1111 100 0001 0000 000
B1 AArch32 system registers
B1.67 Hyp System Control Register
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-257
Non-Confidential
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