B2.50 Hyp System Trap Register, EL2
The HSTR_EL2 characteristics are:
Purpose
Controls access to ThumbEE and coprocessor registers at lower exception levels in AArch32.
Usage constraints
This register is accessible as follows:
EL0 EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - - RW RW RW
Configurations
HSTR_EL2 is architecturally mapped to AArch32 register HSTR. See B1.69 Hyp System Trap
Register on page B1-259.
Attributes
HSTR_EL2 is a 32-bit register.
31 0
RES0
1234567891011121314151617
TTEE
RES0
T15
T13
T12
T11
T10
T9
T8
T0
T1
T2
T3
RES0
T5
T6
T7
Figure B2-24 HSTR_EL2 bit assignments
[31:17]
Reserved, RES0.
TTEE, [16]
Trap T32EE. This value is:
0 T32EE is not supported.
T15, [15]
Trap coprocessor primary register CRn = 15. The possible values are:
0 Has no effect on Non-secure accesses to CP15 registers.
1 Trap valid Non-secure accesses to coprocessor primary register CRn = 15 to Hyp mode.
The reset value is 0.
[14]
Reserved, RES0.
T13, [13]
B2 AArch64 system registers
B2.50 Hyp System Trap Register, EL2
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-441
Non-Confidential
To Next Page
Loading...
Need help?
General
