ARM Cortex-A35

B2.81 Monitor Debug Configuration Register, EL3
The MDCR_EL3 characteristics are:
Purpose
Provides configuration options for Security to self-hosted debug.
Usage constraints
This register is accessible as follows:
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - - - RW RW
Configurations
MDCR_EL3 is mapped to AArch32 register SDCR. See B1.106 Secure Debug Control Register
on page B1-335.
Attributes
MDCR_EL3 is a 32-bit register.
31 0
RES0
TPM
20 192122 16 151718 14 13 11 10 9 678 5
RES0
TDA
TDOSA
SPD32
SDD
SPME
EDAD
EPMAD
RES0 RES0 RES0
Figure B2-51 MDCR_EL3 bit assignments
[31:22]
Reserved, RES0.
EPMAD, [21]
External debugger access to Performance Monitors registers disabled. This disables access to
these registers by an external debugger. The possible values are:
0 Access to Performance Monitors registers from external debugger is permitted.
1 Access to Performance Monitors registers from external debugger is disabled, unless
overridden by authentication interface.
EDAD, [20]
External debugger access to breakpoint and watchpoint registers disabled. This disables access
to these registers by an external debugger. The possible values are:
0 Access to breakpoint and watchpoint registers from external debugger is permitted.
1 Access to breakpoint and watchpoint registers from external debugger is disabled, unless
overridden by authentication interface.
[19:18]
Reserved, RES0.
SPME, [17]
Secure performance monitors enable. This enables event counting exceptions from Secure state.
The possible values are:
B2 AArch64 system registers
B2.81 Monitor Debug Configuration Register, EL3
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B2-503
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