ARM Cortex-A35 User Manual

B1.82 Memory Model Feature Register 2
The ID_MMFR2 characteristics are:
Purpose
Provides information about the implemented memory model and memory management support
in AArch32.
Usage constraints
This register is accessible as follows:
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - RO RO RO RO RO
Must be interpreted with ID_MMFR0, ID_MMFR1, and ID_MMFR3. See:
• B1.80 Memory Model Feature Register 0 on page B1-281
• B1.81 Memory Model Feature Register 1 on page B1-283
• B1.83 Memory Model Feature Register 3 on page B1-287
Configurations
ID_MMFR2 is architecturally mapped to AArch64 register ID_MMFR2_EL1. See
B2.65 AArch32 Memory Model Feature Register 2, EL1 on page B2-471.
There is one copy of this register that is used in both Secure and Non-secure states.
Attributes
ID_MMFR2 is a 32-bit register.
31
12 11 8 7 0
HWAccFlg
4 328 27 24 23 20 19 16 15
WFIStall MemBarr UniTLB HvdTLB LL1HvdRng L1HvdBG L1HvdFG
Figure B1-37 ID_MMFR2 bit assignments
HWAccFlg, [31:28]
Hardware Access Flag. Indicates support for a Hardware Access flag, as part of the VMSAv7
implementation:
0x0 Not supported.
WFIStall, [27:24]
Wait For Interrupt Stall. Indicates the support for Wait For Interrupt (WFI) stalling:
0x1 Support for WFI stalling.
MemBarr, [23:20]
Memory Barrier. Indicates the supported CP15 memory barrier operations.
0x2 Supported CP15 memory barrier operations are:
• Data Synchronization Barrier (DSB).
• Instruction Synchronization Barrier (ISB).
• Data Memory Barrier (DMB).
UniTLB, [19:16]
B1 AArch32 system registers
B1.82 Memory Model Feature Register 2
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B1-285
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English