ARM Cortex-A35 User Manual

C8.2 External Debug Reserve Control Register
The EDRCR characteristics are:
Purpose
This register is used to allow imprecise entry to Debug state and clear sticky bits in EDSCR.
This register is part of the Debug registers functional group.
Usage constraints
This register is accessible as follows:
Off DLK OSLK SLK Default
Error Error Error WI WO
Configurations
EDRCR is in the Core power domain.
Attributes
See C8.1 Memory-mapped debug register summary on page C8-644.
EDRCR is a 32-bit register.
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
0000RES0
CBRRQ
CSPA
CSE
Figure C8-1 EDRCR bit assignments
[31:5]
Reserved, RES0.
CBRRQ, [4]
Allow imprecise entry to Debug state. The actions on writing to this bit are:
0 No action.
1 Allow imprecise entry to Debug state, for example by canceling pending bus accesses.
Setting this bit to 1 allows a debugger to request imprecise entry to Debug state. An
External Debug Request debug event must be pending before the debugger sets this bit
to 1.
CSPA, [3]
Clear Sticky Pipeline Advance. This bit is used to clear the EDSCR.PipeAdv bit to 0. The
actions on writing to this bit are:
0 No action.
1 Clear the EDSCR.PipeAdv bit to 0.
CSE, [2]
Clear Sticky Error. Used to clear the EDSCR cumulative error bits to 0. The actions on writing
to this bit are:
0 No action
C8 Memory-mapped debug registers
C8.2 External Debug Reserve Control Register
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English