1 Clear the EDSCR.{TXU, RXO, ERR} bits, and, if the processor is in Debug state, the
EDSCR.ITO bit, to 0.
[1:0]
Reserved, RES0.
The EDRCR can be accessed through the external debug interface, offset 0x090.
C8 Memory-mapped debug registers
C8.2 External Debug Reserve Control Register
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reserved.
C8-649
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