C8.16 External Debug Component Identification Register 0
The EDCIDR0 characteristics are:
Purpose
Provides information to identify an external debug component.
Usage constraints
This register is accessible as follows:
Off DLK OSLK EDAD SLK Default
- - - - - RO
Table C1-1 Conditions on external register access to debug registers on page C1-579 describes
the condition codes.
Configurations
The EDCIDR0 is in the Debug power domain.
Attributes
See C8.1 Memory-mapped debug register summary on page C8-644.
RES0
31 0
PRMBL_0
78
Figure C8-12 EDCIDR0 bit assignments
[31:8]
Reserved, RES0.
PRMBL_0, [7:0]
0x0D Preamble byte 0.
The EDCIDR0 can be accessed through the external debug interface, offset 0xFF0.
C8 Memory-mapped debug registers
C8.16 External Debug Component Identification Register 0
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
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C8-665
Non-Confidential
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