ARM Cortex-A35 User Manual

B2.65 AArch32 Memory Model Feature Register 2, EL1
The ID_MMFR2_EL1 characteristics are:
Purpose
Provides information about the implemented memory model and memory management support
in AArch32.
Usage constraints
This register is accessible as follows:
EL0 EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- RO RO RO RO RO
Configurations
ID_MMFR2_EL1 is architecturally mapped to AArch32 register ID_MMFR2. See
B1.82 Memory Model Feature Register 2 on page B1-285.
Attributes
ID_MMFR2_EL1 is a 32-bit register.
31
12 11 8 7 0
HWAccFlg
4 328 27 24 23 20 19 16 15
WFIStall MemBarr UniTLB HvdTLB LL1HvdRng L1HvdBG L1HvdFG
Figure B2-38 ID_MMFR2_EL1 bit assignments
HWAccFlg, [31:28]
Hardware access flag. Indicates support for a hardware access flag, as part of the VMSAv7
implementation:
0x0 Not supported.
WFIStall, [27:24]
Wait For Interrupt Stall. Indicates the support for Wait For Interrupt (WFI) stalling:
0x1 Support for WFI stalling.
MemBarr, [23:20]
Memory Barrier. Indicates the supported CP15 memory barrier operations.
0x2 Supported CP15 memory barrier operations are:
• Data Synchronization Barrier (DSB).
• Instruction Synchronization Barrier (ISB).
• Data Memory Barrier (DMB).
UniTLB, [19:16]
Unified TLB. Indicates the supported TLB maintenance operations, for a unified TLB
implementation.
B2 AArch64 system registers
B2.65 AArch32 Memory Model Feature Register 2, EL1
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-471
Non-Confidential

ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English