ARM Cortex-A35

Indicates the supported L1 cache line maintenance operations by set/way, for a Harvard cache
implementation:
0x0 None supported.
L1UniVA, [7:4]
Indicates the supported L1 cache line maintenance operations by MVA, for a unified cache
implementation:
0x0 None supported.
L1HvdVA, [3:0]
Indicates the supported L1 cache line maintenance operations by MVA, for a Harvard cache
implementation:
0x0 None supported.
To access the ID_MMFR1_EL1:
MRS <Xt>, ID_MMFR1_EL1 ; Read ID_MMFR1_EL1 into Xt
Register access is encoded as follows:
Table B2-56 ID_MMFR1_EL1 access encoding
op0 op1 CRn CRm op2
11 000 0000 0001 101
B2 AArch64 system registers
B2.64 AArch32 Memory Model Feature Register 1, EL1
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-470
Non-Confidential