C8.3 External Debug Integration Mode Control Register
The EDITCTRL characteristics are:
Purpose
Enables the external debug to switch from its default mode into integration mode, where test
software can control directly the inputs and outputs of the processor, for integration testing or
topology detection.
Usage constraints
This register is accessible as follows:
Off DLK OSLK EDAD SLK Default
- - - - RO RW
Table C1-1 Conditions on external register access to debug registers on page C1-579 describes
the condition codes.
Configurations
EDITCTRL is in the processor power domain.
Attributes
See C8.1 Memory-mapped debug register summary on page C8-644.
RES0
31 1 0
IME
Figure C8-2 EDITCTRL bit assignments
[31:1]
Reserved, RES0.
IME, [0]
Integration Mode Enable.
RES0. The device does not revert to an integration mode to enable integration testing or
topology detection.
The EDITCTRL can be accessed through the external debug interface, offset 0xF00.
C8 Memory-mapped debug registers
C8.3 External Debug Integration Mode Control Register
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
C8-650
Non-Confidential
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