B2.66 AArch32 Memory Model Feature Register 3, EL1
The ID_MMFR3_EL1 characteristics are:
Purpose
Provides information about the memory model and memory management support in AArch32.
Usage constraints
This register is accessible as follows:
EL0 EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- RO RO RO RO RO
Configurations
ID_MMFR3_EL1 is architecturally mapped to AArch32 register ID_MMFR3. See
B1.83 Memory Model Feature Register 3 on page B1-287.
Attributes
ID_MMFR3_EL1 is a 32-bit register.
31
12 11 8 7 04 328 27 24 23 20 19 16 15
ReservedCohWalkCMemSzSupersec MaintBcst BPMaint CMaintSW CMaintVA
Figure B2-39 ID_MMFR3_EL1 bit assignments
Supersec, [31:28]
Supersections. Indicates support for supersections:
0x0 Supersections supported.
CMemSz, [27:24]
Cached memory size. Indicates the size of physical memory supported by the processor caches:
0x2 1TByte, corresponding to a 40-bit physical address range.
CohWalk, [23:20]
Coherent walk. Indicates whether translation table updates require a clean to the point of
unification:
0x1 Updates to the translation tables do not require a clean to the point of unification to
ensure visibility by subsequent translation table walks.
[19:16]
Reserved, RES0.
MaintBcst, [15:12]
Maintenance broadcast. Indicates whether cache, TLB and branch predictor operations are
broadcast:
0x2 Cache, TLB and branch predictor operations affect structures according to shareability
and defined behavior of instructions.
BPMaint, [11:8]
Branch predictor maintenance. Indicates the supported branch predictor maintenance operations.
B2 AArch64 system registers
B2.66 AArch32 Memory Model Feature Register 3, EL1
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-473
Non-Confidential
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