ARM Cortex-A35 User Manual

0x6 Supported unified TLB maintenance operations are:
• Invalidate all entries in the TLB.
• Invalidate TLB entry by MVA.
• Invalidate TLB entries by ASID match.
• Invalidate instruction TLB and data TLB entries by MVA All ASID. This is a
shared unified TLB operation.
• Invalidate Hyp mode unified TLB entry by MVA.
• Invalidate entire Non-secure EL1 and EL0 unified TLB.
• Invalidate entire Hyp mode unified TLB.
• TLBIMVALIS, TLBIMVAALIS, TLBIMVALHIS, TLBIMVAL, TLBIMVAAL, and TLBIMVALH.
• TLBIIPAS2IS, TLBIIPAS2LIS, TLBIIPAS2, and TLBIIPAS2L.
HvdTLB, [15:12]
Harvard TLB. Indicates the supported TLB maintenance operations, for a Harvard TLB
implementation:
0x0 Not supported.
LL1HvdRng, [11:8]
L1 Harvard cache Range. Indicates the supported L1 cache maintenance range operations, for a
Harvard cache implementation:
0x0 Not supported.
L1HvdBG, [7:4]
L1 Harvard cache Background fetch. Indicates the supported L1 cache background prefetch
operations, for a Harvard cache implementation:
0x0 Not supported.
L1HvdFG, [3:0]
L1 Harvard cache Foreground fetch. Indicates the supported L1 cache foreground prefetch
operations, for a Harvard cache implementation:
0x0 Not supported.
To access the ID_MMFR2_EL1:
MRS <Xt>, ID_MMFR2_EL1 ; Read ID_MMFR2_EL1 into Xt
Register access is encoded as follows:
Table B2-57 ID_MMFR2_EL1 access encoding
op0 op1 CRn CRm op2
11 000 0000 0001 110
B2 AArch64 system registers
B2.65 AArch32 Memory Model Feature Register 2, EL1
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-472
Non-Confidential

ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English