ARM Cortex-A35 User Manual

B2.91 System Control Register, EL2
The SCTLR_EL2 characteristics are:
Purpose
Provides top level control of the system, including its memory system at EL2.
SCTLR_EL2 is part of:
• The Virtual memory control registers functional group.
• The Hypervisor and virtualization registers functional group.
Usage constraints
This register is accessible as follows:
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - - RW RW RW
Configurations
SCTLR_EL2 is architecturally mapped to AArch32 register HSCTLR. See B1.67 Hyp System
Control Register on page B1-254.
Attributes
SCTLR_EL2 is a 32-bit register.
31
0
EE
2526 20
RES1
19 18 12 11 2 14 3
WXN
I C A M
SA
RES0
30 29 28 27
RES1 RES0
24 23
RES0
22 21
RES0
17 16 15 14 13
RES1
RES0
RES1
RES0
10 6 5
RES0 RES1
RES1
Figure B2-62 SCTLR_EL2 bit assignments
[31:30]
Reserved, RES0.
[29:28]
Reserved, RES1.
[27:26]
Reserved, RES0.
EE, [25]
Exception endianness. The possible values are:
0 Little endian.
1 Big endian.
The reset value depends on the value of the CFGEND configuration input.
[24]
Reserved, RES0.
[23:22]
Reserved, RES1.
[21:20]
Reserved, RES0.
B2 AArch64 system registers
B2.91 System Control Register, EL2
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-529
Non-Confidential

ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English