ARM Cortex-A35 User Manual

B2.10 AArch64 Performance monitor registers
The following table shows the performance monitor registers in AArch64 state.
Bits[63:32] are reset to 0x00000000 for all 64-bit registers in the table.
Table B2-10 AArch64 performance monitor registers
Name Type Reset Width Description
PMCR_EL0 RW
0x410A3000
32 C10.6 Performance Monitors Control Register, EL0 on page C10-704
PMCNTENSET_EL0 RW UNK 32
Performance Monitors Count Enable Set Register
See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture
profile for more information.
PMCNTENCLR_EL0 RW UNK 32
Performance Monitors Count Enable Clear Register
See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture
profile for more information.
PMOVSCLR_EL0 RW UNK 32
Performance Monitors Overflow Flag Status Clear Register
See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture
profile for more information.
PMSWINC_EL0 WO - 32
Performance Monitors Software Increment Register
See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture
profile for more information.
PMSELR_EL0 RW UNK 32
Performance Monitors Event Counter Selection Register
See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture
profile for more information.
PMCEID0_EL0 RO
0x6FFFBFFF
32
C10.7 Performance Monitors Common Event Identification Register 0, EL0
on page C10-707
The reset value is 0x6E3FBFFF if the Cortex‑A35 processor has not been
configured with an L2 cache.
PMCEID1_EL0 RO
0x00000000
32
C10.8 Performance Monitors Common Event Identification Register 1, EL0
on page C10-711
See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture
profile for more information.
PMCCNTR_EL0 RW UNK 64
Performance Monitors Cycle Counter
See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture
profile for more information.
PMXEVTYPER_EL0 RW UNK 32
Performance Monitors Selected Event Type and Filter Register
See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture
profile for more information.
PMXEVCNTR_EL0 RW UNK 32
Performance Monitors Selected Event Counter Register
See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture
profile for more information.
B2 AArch64 system registers
B2.10 AArch64 Performance monitor registers
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English