ARM Cortex-A35 User Manual

Table B2-10 AArch64 performance monitor registers (continued)
Name Type Reset Width Description
PMUSERENR_EL0 RW
0x00000000
32
Performance Monitors User Enable Register
See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture
profile for more information.
PMINTENSET_EL1 RW UNK 32
Performance Monitors Interrupt Enable Set Register
See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture
profile for more information.
PMINTENCLR_EL1 RW UNK 32
Performance Monitors Interrupt Enable Clear Register
See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture
profile for more information.
PMOVSSET_EL0 RW UNK 32
Performance Monitors Overflow Flag Status Set Register
See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture
profile for more information.
PMEVCNTR0_EL0 RW UNK 32 Performance Monitor Event Count Registers
PMEVCNTR1_EL0 RW UNK 32
PMEVCNTR2_EL0 RW UNK 32
PMEVCNTR3_EL0 RW UNK 32
PMEVCNTR4_EL0 RW UNK 32
PMEVCNTR5_EL0 RW UNK 32
PMEVTYPER0_EL0 RW UNK 32
Performance Monitor Event Type Registers
PMEVTYPER1_EL0 RW UNK 32
PMEVTYPER2_EL0 RW UNK 32
PMEVTYPER3_EL0 RW UNK 32
PMEVTYPER4_EL0 RW UNK 32
PMEVTYPER5_EL0 RW UNK 32
PMCCFILTR_EL0 RW
0x00000000
32
Performance Monitors Cycle Count Filter Register
See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture
profile for more information.
B2 AArch64 system registers
B2.10 AArch64 Performance monitor registers
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English