B2.100 Vector Base Address Register, EL1
The VBAR_EL1 characteristics are:
Purpose
Holds the exception base address for any exception that is taken to EL1.
Usage constraints
This register is accessible as follows:
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- RW RW RW RW RW
Configurations
The VBAR_EL1[31:0] is architecturally mapped to the Non-secure AArch32 VBAR register.
See B1.119 Vector Base Address Register on page B1-354.
Attributes
VBAR_EL1 is a 64-bit register.
63 0
RES0
11 10
Vector base address
Figure B2-71 VBAR_EL1 bit assignments
Vector base address, [63:11]
Base address of the exception vectors for exceptions taken in this exception level.
[10:0]
Reserved, RES0.
To access the VBAR_EL1:
MRS <Xt>, VBAR_EL1 ; Read VBAR_EL1 into Xt
MSR VBAR_EL1, <Xt> ; Write Xt to VBAR_EL1
Register access is encoded as follows:
Table B2-93 VBAR_EL1 access encoding
op0 op1 CRn CRm op2
11 000 1100 0000 000
B2 AArch64 system registers
B2.100 Vector Base Address Register, EL1
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-551
Non-Confidential
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