B1.19 64-bit registers
The processor can access 64-bit wide CP15 system registers in AArch32 state.
The following table shows the 64-bit wide CP15 system registers, accessed by the MCRR and MRRC
instructions. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile for
more information.
Table B1-18 64-bit register summary
Op1 CRm Name Reset Description
0 c2 TTBR0 UNK Translation Table Base Register 0
1 c2 TTBR1 UNK Translation Table Base Register 1
4 c2 HTTBR UNK
Hyp Translation Table Base Register
6 c2 VTTBR UNK
Virtualization Translation Table Base Register
0 c7 PAR UNK B1.100 Physical Address Register on page B1-321
0 c14 CNTPCT UNK
Physical Timer Count Register
1 c14 CNTVCT UNK
Virtual Timer Count Register
2 c14 CNTP_CVAL UNK
Physical Timer CompareValue Register
3 c14 CNTV_CVAL UNK
Virtual Timer CompareValue Register
4 c14 CNTVOFF UNK
Virtual Timer Offset Register
6 c14 CNTHP_CVAL UNK
Physical Timer CompareValue Register
0 c15 CPUACTLR
0x00000000090CA000
B1.42 CPU Auxiliary Control Register on page B1-208
1 c15 CPUECTLR
0x0000000000000000
B1.43 CPU Extended Control Register on page B1-212
2 c15 CPUMERRSR - B1.44 CPU Memory Error Syndrome Register on page B1-214
3 c15 L2MERRSR - B1.94 L2 Memory Error Syndrome Register on page B1-307
B1 AArch32 system registers
B1.19 64-bit registers
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
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B1-175
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