ARM Cortex-A35 User Manual

B1.95 Memory Attribute Indirection Registers 0 and 1
The MAIR0 and MAIR1 characteristics are:
Purpose
To provide the memory attribute encodings corresponding to the possible AttrIndx values in a
Long-descriptor format translation table entry for stage 1 translations.
Usage constraints
These registers are accessible as follows:
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - RW RW RW RW RW
Accessible only when using the Long-descriptor translation table format. When using the Short-
descriptor format see, instead, B1.101 Primary Region Remap Register on page B1-322 and
B1.99 Normal Memory Remap Register on page B1-319.
AttrIndx[2], from the translation table descriptor, selects the appropriate MAIR. Setting
AttrIndx[2] to 0 selects MAIR0 and setting AttrIndx[2] to 1 selects MAIR1.
The Secure instance of the register gives the value for memory accesses from Secure state.
The Non-secure instance of the register gives the value for memory accesses from Non-secure
states other than Hyp mode.
Configurations
MAIR0 (NS) is architecturally mapped to AArch64 register MAIR_EL1[31:0] when
TTBCR.EAE==1. See B2.77 Memory Attribute Indirection Register, EL1 on page B2-496.
MAIR0 (S) is mapped to AArch64 register MAIR_EL3[31:0] when TTBCR.EAE==1. See
B2.79 Memory Attribute Indirection Register, EL3 on page B2-499.
MAIR1 (NS) is architecturally mapped to AArch64 register MAIR_EL1[63:32] when
TTCR.EAE==1. See B2.77 Memory Attribute Indirection Register, EL1 on page B2-496.
MAIR1 (S) is mapped to AArch64 register MAIR_EL3[63:32] when TTBCR.EAE==1. See
B2.79 Memory Attribute Indirection Register, EL3 on page B2-499.
If EL3 is using AArch32, there are separate Secure and Non-secure instances of this register.
If EL3 is using AArch32, write access to MAIR0(S) and MAIR1(S) is disabled when the
CP15SDISABLE2 signal is asserted HIGH.
Attributes
MAIR0 is a 32-bit register when TTBCR.EAE==1.
Attr7
Attr6 Attr5 Attr4
Attr3
31 24 23 16 15 8 7 0
Attr2 Attr1 Attr0MAIR0
MAIR1
Figure B1-49 MAIR0 and MAIR1 bit assignments
B1 AArch32 system registers
B1.95 Memory Attribute Indirection Registers 0 and 1
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English