ARM Cortex-A35 User Manual

• If two or more first memory error events from different RAMs occur in the same cycle, one of the
errors is selected arbitrarily, while the Other error count field is incremented only by one.
• If two or more memory error events from different RAMs, that do not match the RAMID, bank, way,
or index information in this register while the sticky Valid bit is set, occur in the same cycle, the
Other error count field is incremented only by one.
To access the L2MERRSR:
MRRC p15, 3, <Rt>, <Rt2>, c15; Read L2MERRSR into Rt and Rt2
MCRR p15, 3, <Rt>, <Rt2>, c15; Write Rt and Rt2 to L2MERRSR
Register access is encoded as follows:
Table B1-75 L2MERRSR access encoding
coproc opc1 CRm
1111 0011 1111
B1 AArch32 system registers
B1.94 L2 Memory Error Syndrome Register
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B1-309
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English