ARM Cortex-A35 User Manual

B2.20 Auxiliary Control Register, EL2
The ACTLR_EL2 characteristics are:
Purpose
Controls write access to IMPLEMENTATION DEFINED registers in Non-secure EL1 modes, such as
CPUACTLR, CPUECTLR, L2CTLR, L2ECTLR, and L2ACTLR.
Usage constraints
This register is accessible as follows:
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - - RW RW RW
Configurations
The ACTLR_EL2 is architecturally mapped to the AArch32 HACTLR register. See B1.55 Hyp
Auxiliary Control Register on page B1-231.
Attributes
ACTLR_EL2 is a 32-bit register.
31 0
RES0
L2ACTLR_EL1 access control
1234567
L2ECTLR_EL1 access control
L2CTLR_EL1 access control
CPUECTLR_EL1 access control
CPUACTLR_EL1 access control
RES0
Figure B2-1 ACTLR_EL2 bit assignments
[31:7]
Reserved, RES0.
L2ACTLR_EL1 access control, [6]
L2ACTLR_EL1 write access control. The possible values are:
0 The register is not write accessible from Non-secure EL1.This is the reset value.
1 The register is write accessible from Non-secure EL1.
Write access from Non-secure EL1 also requires ACTLR_EL3[6] to be set.
L2ECTLR_EL1 access control, [5]
L2ECTLR_EL1 write access control. The possible values are:
0 The register is not write accessible from Non-secure EL1.This is the reset value.
1 The register is write accessible from Non-secure EL1.
Write access from Non-secure EL1 also requires ACTLR_EL3[5] to be set.
L2CTLR_EL1 access control, [4]
L2CTLR_EL1 write access control. The possible values are:
0 The register is not write accessible from Non-secure EL1.This is the reset value.
B2 AArch64 system registers
B2.20 Auxiliary Control Register, EL2
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English