ARM Cortex-A35 User Manual

B2.64 AArch32 Memory Model Feature Register 1, EL1
The ID_MMFR1_EL1 characteristics are:
Purpose
Provides information about the memory model and memory management support in AArch32.
Usage constraints
This register is accessible as follows:
EL0 EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- RO RO RO RO RO
Configurations
ID_MMFR1_EL1 is architecturally mapped to AArch32 register ID_MMFR1. See
B1.81 Memory Model Feature Register 1 on page B1-283.
Attributes
ID_MMFR1_EL1 is a 32-bit register.
BPred L1TstCln L1Uni L1Hvd L1UniSW L1HvdSW L1UniVA L1HvdVA
31 28 27 24 23 20 19 16 15 12 11 8 7 4 3
0
Figure B2-37 ID_MMFR1_EL1 bit assignments
BPred, [31:28]
Indicates branch predictor management requirements:
0x4 For execution correctness, branch predictor requires no flushing at any time.
L1TstCln, [27:24]
Indicates the supported L1 Data cache test and clean operations, for Harvard or unified cache
implementation:
0x0 None supported.
L1Uni, [23:20]
Indicates the supported entire L1 cache maintenance operations, for a unified cache
implementation:
0x0 None supported.
L1Hvd, [19:16]
Indicates the supported entire L1 cache maintenance operations, for a Harvard cache
implementation:
0x0 None supported.
L1UniSW, [15:12]
Indicates the supported L1 cache line maintenance operations by set/way, for a unified cache
implementation:
0x0 None supported.
L1HvdSW, [11:8]
B2 AArch64 system registers
B2.64 AArch32 Memory Model Feature Register 1, EL1
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B2-469
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English