A1.2 Features
The Cortex‑A35 processor includes the following features:
• Full implementation of the Armv8-A A64, A32, and T32 instruction sets.
• Both the AArch32 and AArch64 execution states at all Exception levels (EL0 to EL3).
• In-order pipeline with direct and indirect branch prediction.
• Separate Level 1 (L1) data and instruction side memory systems with a Memory Management Unit
(MMU).
• Level 2 (L2) memory system that provides cluster memory coherency.
• Optional L2 cache.
• Cache protection in the form of Error Correction Code (ECC) or parity on all RAM instances, except
for the L2 victim RAM. There are two implementation options:
— CPU cache protection.
— Snoop Control Unit (SCU)-L2 cache protection.
• TrustZone
®
.
• Optional data engine that implements the Advanced SIMD and floating-point architecture support.
• Optional Cryptographic Extension. This architectural extension is only available if the data engine is
present.
• Armv8 debug logic.
• Performance Monitoring Unit (PMU).
• Optional Embedded Trace Macrocell (ETM) that supports instruction trace only.
• Optional Generic Interrupt Controller (GIC) CPU interface to connect to an external distributor.
• Generic Timers supporting 64-bit count input from an external system counter.
Related information
A1.3 Implementation options on page A1-32
A1.4 Supported standards and specifications on page A1-34
A6.1 About the L1 memory system on page A6-90
A7.1 About the L2 memory system on page A7-98
A5.7 About cache protection on page A5-84
A1 Introduction
A1.2 Features
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
A1-31
Non-Confidential
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