ARM Cortex-A35 User Manual

B1.94 L2 Memory Error Syndrome Register
The L2MERRSR characteristics are:
Purpose
Holds ECC errors on the:
• L2 data RAMs.
• L2 tag RAMs.
• SCU snoop filter RAMs.
Usage constraints
This register is accessible as follows:
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - RW RW RW RW RW
Configurations
The L2MERRSR is mapped to the AArch64 L2MERRSR_EL1 register. See B2.76 L2 Memory
Error Syndrome Register, EL1 on page B2-493.
There is one copy of this register that is used in both Secure and Non-secure states.
A write of any value to the register updates the register to 0x0000000000000000.
Attributes
L2MERRSR is a a 64-bit register.
Fatal
24 23 22 21
Other error
count
Repeat error
count
3132 063
RES0
4748 40 39 30
Valid
RAMID
18 17
CPUID/Way
RAM address
2362
RES0RES0
16
RES0
Figure B1-48 L2MERRSR bit assignments
Fatal, [63]
Fatal bit. This bit is set to 1 on the first memory error that caused a data abort. It is a sticky bit
so that after it is set, it remains set until the register is written.
The reset value is 0.
[62:48]
Reserved, RES0.
Other error count, [47:40]
This field is set to 0 on the first memory error and is incremented on any memory error that does
not match the RAMID and Bank/Way information in this register while the sticky Valid bit is
set.
The reset value is 0.
Repeat error count, [39:32]
This field is set to 0 on the first memory error and is incremented on any memory error that
exactly matches the RAMID and Bank/Way information in this register while the sticky Valid
bit is set.
The reset value is 0.
B1 AArch32 system registers
B1.94 L2 Memory Error Syndrome Register
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English