C12.4 CTI Integration Mode Control Register
The CTIITCTRL characteristics are:
Purpose
The CTIITCTRL shows that the Cortex‑A35 processor does not implement an integration mode.
Usage constraints
The accessibility of CTIITCTRL by condition code is:
Off DLK OSLK EDAD SLK Default
- - - - RO/WI RW
C12.2 External register access permissions to the CTI registers on page C12-828 describes the
condition codes.
Configurations
CTIITCTRL is in the Debug power domain.
Attributes
See the register summary in C12.1 Cross trigger register summary on page C12-826.
31 0
1
RES0
IME
Figure C12-2 CTIITCTRL bit assignments
[31:1]
Reserved, RES0.
IME, [0]
Integration mode enable. The possible value is:
0 Normal operation.
CTIITCTRL can be accessed through the external debug interface, offset 0xF00.
C12 CTI registers
C12.4 CTI Integration Mode Control Register
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
C12-831
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