ARM Cortex-A35 User Manual

B2.95 Translation Control Register, EL2
The TCR_EL2 characteristics are:
Purpose
Controls translation table walks required for stage 1 translation of a memory access from EL2
and holds cacheability and shareability information.
TCR_EL2 is part of:
• The Virtual memory control registers functional group.
• The Hypervisor and virtualization registers functional group.
Usage constraints
This register is accessible as follows:
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - - RW RW RW
Configurations
TCR_EL2 is architecturally mapped to AArch32 register HCTR. See B1.70 Hyp Translation
Control Register on page B1-263.
Attributes
TCR_EL2 is a 32-bit register.
31
30 24 23 22 21 20 19 18 16 15 14 13 12 11 10 9 8 7 6 5
0
RES0SH0TG0PS
IRGN0
ORGN0
T0SZ
RES0
TBI
RES0
RES1RES1
RES0
Figure B2-66 TCR_EL2 bit assignments
[31]
Reserved, RES1.
[30:24]
Reserved, RES0.
[23]
Reserved, RES1.
[22:21]
Reserved, RES0.
TBI, [20]
Top Byte Ignored. Indicates whether the top byte of the input address is used for address match.
The possible values are:
0 Top byte used in the address calculation.
1 Top byte ignored in the address calculation.
[19]
Reserved, RES0.
PS, [18:16]
B2 AArch64 system registers
B2.95 Translation Control Register, EL2
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-540
Non-Confidential

ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English