ARM Cortex-A35 User Manual

Physical address size. The possible values are:
0b000 32 bits, 4GB.
0b001 36 bits, 64GB.
0b010 40 bits, 1TB.
Other values are reserved.
TG0, [15:14]
TTBR0_EL2 granule size. The possible values are:
0b00 4KB.
0b10 16KB.
0b01 64KB.
0b11 Reserved.
All other values are not supported.
SH0, [13:12]
Shareability attribute for memory associated with translation table walks using TTBR0_EL2.
The possible values are:
0b00 Non-shareable.
0b01 Reserved.
0b10 Outer shareable.
0b11 Inner shareable.
ORGN0, [11:10]
Outer cacheability attribute for memory associated with translation table walks using
TTBR0_EL2. The possible values are:
0b00 Normal memory, Outer Non-cacheable.
0b01 Normal memory, Outer Write-Back Write-Allocate Cacheable.
0b10 Normal memory, Outer Write-Through Cacheable.
0b11 Normal memory, Outer Write-Back no Write-Allocate Cacheable.
IRGN0, [9:8]
Inner cacheability attribute for memory associated with translation table walks using
TTBR0_EL2. The possible values are:
0b00 Normal memory, Inner Non-cacheable.
0b01 Normal memory, Inner Write-Back Write-Allocate Cacheable.
0b10 Normal memory, Inner Write-Through Cacheable.
0b11 Normal memory, Inner Write-Back no Write-Allocate Cacheable.
[7:6]
Reserved, RES0.
T0SZ, [5:0]
Size offset of the memory region addressed by TTBR0_EL2. The region size is 2
(64-T0SZ)
bytes.
To access the TCR_EL2:
MRS <Xt>, TCR_EL2 ; Read EL2 Translation Control Register
MSR TCR_EL2, <Xt> ; Write EL2 Translation Control Register
B2 AArch64 system registers
B2.95 Translation Control Register, EL2
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English