ARM Cortex-A35 User Manual

B2.29 Cache Size ID Register, EL1
The CCSIDR_EL1 characteristics are:
Purpose
Provides information about the architecture of the caches.
Usage constraints
This register is accessible as follows:
EL0 EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- RO RO RO RO RO
Configurations
CCSIDR_EL1 is architecturally mapped to AArch32 register CCSIDR. See B1.39 Cache Size
ID Register on page B1-201.
Attributes
CCSIDR_EL1 is a 32-bit register.
WB
31 28 27 12 3 0
RA
LineSizeWT
30 29 13 2
WA
NumSets Associativity
Figure B2-4 CCSIDR_EL1 bit assignments
WT, [31]
Indicates support for write-through:
0 Cache level does not support write-through.
WB, [30]
Indicates support for write-back:
0 Cache level does not support write-back.
1 Cache level supports write-back.
RA, [29]
Indicates support for Read-Allocation:
0 Cache level does not support Read-Allocation.
1 Cache level supports Read-Allocation.
WA, [28]
Indicates support for Write-Allocation:
0 Cache level does not support Write-Allocation.
1 Cache level supports Write-Allocation.
B2 AArch64 system registers
B2.29 Cache Size ID Register, EL1
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B2-398
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English