B1.101 Primary Region Remap Register
The PRRR characteristics are:
Purpose
Controls the top level mapping of the TEX[0], C, and B memory region attributes.
Usage constraints
This register is accessible as follows:
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - RW RW RW RW RW
PRRR is not accessible when the Long-descriptor translation table format is in use. See, instead,
B1.95 Memory Attribute Indirection Registers 0 and 1 on page B1-310.
Configurations
PRRR (NS) is architecturally mapped to AArch64 register MAIR_EL1[31:0] when
TTBCR.EAE is 0. See B2.77 Memory Attribute Indirection Register, EL1 on page B2-496.
PRRR (S) is mapped to AArch64 register MAIR_EL3[31:0] when TTBCR.EAE is 0. See
B2.79 Memory Attribute Indirection Register, EL3 on page B2-499.
If EL3 is using AArch32, there are separate Secure and Non-secure instances of this register.
If EL3 is using AArch32, write access to PRRR(S) is disabled when the CP15SDISABLE2
signal is asserted HIGH.
Attributes
PRRR is a 32-bit register when TTBCR.EAE==0.
31
30 29 28 27 26 25 24 23 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RES0 TR7 TR6 TR5 TR4 TR3 TR2 TR1 TR0
DS0
DS1
NS1
NS0
NOS0
NOS1
NOS2
NOS3
NOS7
NOS6
NOS5
NOS4
Figure B1-54 PRRR bit assignments
NOSn, [24+n]
Outer Shareable property mapping for memory attributes n, where n is 0-7, if the region is
mapped as Normal Shareable. n is the value of the TEX[0], C and B bits concatenated. The
possible values of each NOSn bit are:
0 Memory region is Outer Shareable.
1 Memory region is Inner Shareable.
The value of this bit is ignored if the region is Normal or Device memory that is not Shareable.
[23:20]
Reserved, RES0.
NS1, [19]
B1 AArch32 system registers
B1.101 Primary Region Remap Register
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-322
Non-Confidential
To Next Page
Loading...
Need help?
General
