ARM Cortex-A35 User Manual

C11.8 Event Control 1 Register
The TRCEVENTCTL1R characteristics are:
Purpose
Controls the behavior of the events that TRCEVENTCTL0R selects.
Usage constraints
• You must always program this register as part of trace unit initialization.
• Accepts writes only when the trace unit is disabled.
Configurations
Available in all configurations.
Attributes
TRCEVENTCTL1R is a 32-bit RW trace register.
See C11.1 ETM register summary on page C11-733.
31 0
RES0
4 358 7
EN
12 11 10
RES0
ATB
13
LPOVERRIDE
Figure C11-7 TRCEVENTCL1R bit assignments
[31:13]
Reserved, RES0.
LPOVERRIDE, [12]
Low-power state behavior override:
0 Low-power state behavior unaffected.
1 Low-power state behavior overridden. The resources and Event trace generation are
unaffected by entry to a low-power state.
ATB, [11]
ATB trigger enable:
0 ATB trigger disabled.
1 ATB trigger enabled.
[10:4]
Reserved, RES0.
EN, [3:0]
One bit per event, to enable generation of an event element in the instruction trace stream when
the selected event occurs:
0 Event does not cause an event element.
1 Event causes an event element.
The TRCEVENTCTL1R can be accessed through the external debug interface, offset 0x024.
C11 ETM registers
C11.8 Event Control 1 Register
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C11-745
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English