C6.6 Debug Device ID Register 1
The DBGDEVID1 characteristics are:
Purpose
Adds to the information given by the DBGDIDR by describing other features of the debug
implementation.
Usage constraints
This register is accessible as follows:
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - RO RO RO RO RO
Configurations
There is one copy of this register that is used in both Secure and Non-secure states.
Attributes
See C6.1 AArch32 debug register summary on page C6-620.
RES0
31 0
PCSROffset
4 3
Figure C6-5 DBGDEVID1 bit assignments
[31:4]
Reserved, RES0.
PCSROffset, [3:0]
Indicates the offset applied to PC samples returned by reads of EDPCSR. The value is:
0x2 EDPCSR samples have no offset applied and do not sample the instruction set state in the
AArch32 state.
To access the DBGDEVID1:
MRC p14, 0, <Rt>, c7, c1, 47 Read Debug Device ID Register 1
C6 AArch32 debug registers
C6.6 Debug Device ID Register 1
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
C6-632
Non-Confidential
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