C10.21 Performance Monitors Component Identification Register 2
The PMCIDR2 characteristics are:
Purpose
Provides information to identify a Performance Monitor component.
Usage constraints
The PMCIDR2 can be accessed through the external debug interface.
The accessibility to the PMCIDR2 by condition code is:
Off DLK OSLK EPMAD SLK Default
- - - - RO RO
C2.2 External register access permissions to the PMU registers on page C2-587 describes the
condition codes.
Configurations
The PMCIDR2 is in the Debug power domain.
Attributes
See the register summary in C10.9 Memory-mapped PMU register summary on page C10-714.
RES0
31 0
PRMBL_2
78
Figure C10-15 PMCIDR2 bit assignments
[31:8]
Reserved, RES0.
PRMBL_2, [7:0]
0x05 Preamble byte 2.
The PMCIDR2 can be accessed through the external debug interface, offset 0xFF8.
C10 PMU registers
C10.21 Performance Monitors Component Identification Register 2
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
C10-729
Non-Confidential
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