B2.101 Vector Base Address Register, EL2
The VBAR_EL2 characteristics are:
Purpose
Holds the exception base address for any exception that is taken to EL2.
Usage constraints
This register is accessible as follows:
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - - RW RW RW
Configurations
The VBAR_EL2[31:0] is architecturally mapped to the AArch32 HVBAR register. See
B1.71 Hyp Vector Base Address Register on page B1-265.
Attributes
VBAR_EL2 is a 64-bit register.
63 0
RES0
11 10
Vector base address
Figure B2-72 VBAR_EL2 bit assignments
Vector base address, [63:11]
Base address of the exception vectors for exceptions taken in this exception level.
[10:0]
Reserved, RES0.
To access the VBAR_EL2:
MRS <Xt>, VBAR_EL2 ; Read VBAR_EL2 into Xt
MSR VBAR_EL2, <Xt> ; Write Xt to VBAR_EL2
Register access is encoded as follows:
Table B2-94 VBAR_EL2 access encoding
op0 op1 CRn CRm op2
11 100 1100 0000 000
B2 AArch64 system registers
B2.101 Vector Base Address Register, EL2
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-552
Non-Confidential
To Next Page
Loading...
Need help?
General
