ARM Cortex-A35 User Manual

B2.78 Memory Attribute Indirection Register, EL2
The MAIR_EL2 characteristics are:
Purpose
Provides the memory attribute encodings corresponding to the possible AttrIndx values in a
Long-descriptor format translation table entry for stage 1 translations at EL2.
Usage constraints
This register is accessible as follows:
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - - RW RW RW
MAIR_EL2 is permitted to be cached in a TLB.
Configurations
MAIR_EL2[31:0] is architecturally mapped to AArch32 register HMAIR0.
MAIR_EL2[63:32] is architecturally mapped to AArch32 register HMAIR1.
Attributes
MAIR_EL2 is a 64-bit register.
The MAIR_EL2 bit assignments follow the same pattern as described in B2.77 Memory Attribute
Indirection Register, EL1 on page B2-496.
To access the MAIR_EL2:
MRS <Xt>, MAIR_EL2 ; Read EL2 Memory Attribute Indirection Register
MSR MAIR_EL2, <Xt> ; Write EL2 Memory Attribute Indirection Register
Register access is encoded as follows:
Table B2-72 MAIR_EL2 access encoding
op0 op1 CRn CRm op2
11 100 1010 0010 000
B2 AArch64 system registers
B2.78 Memory Attribute Indirection Register, EL2
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B2-498
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English