Table B2-69 Attr<n>[3:0] bit assignments
Bits Meaning when Attr<n>[7:4] is 0000 Meaning when Attr<n>[7:4] is not 0000
0b0000
Device-nGnRnE memory UNPREDICTABLE
0b00RW, RW not 00 UNPREDICTABLE Normal Memory, Inner Write-through transient
0b0100
Device-nGnRE memory Normal memory, Inner Non-Cacheable
0b01RW, RW not 00 UNPREDICTABLE Normal Memory, Inner Write-back transient
0b1000
Device-nGRE memory Normal Memory, Inner Write-through non-transient (RW=00)
0b10RW, RW not 00 UNPREDICTABLE Normal Memory, Inner Write-through non-transient
0b1100
Device-GRE memory Normal Memory, Inner Write-back non-transient (RW=00)
0b11RW, RW not 00 UNPREDICTABLE Normal Memory, Inner Write-back non-transient
The following table shows the encoding of the R and W bits that are used, in some Attr<n> encodings in
Table B2-69 Attr<n>[3:0] bit assignments on page B2-497 and Table B2-68 Attr<n>[7:4] bit
assignments on page B2-496, to define the read-allocate and write-allocate policies:
Table B2-70 Encoding of R and W bits in some Attrm fields
R or W Meaning
0 Do not allocate
1 Allocate
To access the MAIR_EL1:
MRS <Xt>, MAIR_EL1 ; Read EL1 Memory Attribute Indirection Register
MSR MAIR_EL1, <Xt> ; Write EL1 Memory Attribute Indirection Register
Register access is encoded as follows:
Table B2-71 MAIR_EL1 access encoding
op0 op1 CRn CRm op2
11 000 1010 0010 000
B2 AArch64 system registers
B2.77 Memory Attribute Indirection Register, EL1
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-497
Non-Confidential
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