A9.5 Attributes of the ACE master interface
The table lists the maximum possible values for the read and write issuing capabilities if the processor
includes four cores.
n Number of cores.
m 1 if the processor is configured for the ACP interface, 0 if it is not.
Table A9-6 ACE master interface attributes
Attribute Value Comments
Write issuing
capability
16 The cluster can issue a maximum of 16 writes:
• Up to 16 writes to Normal memory that is both inner and outer write-back cacheable.
• Up to 15 writes to all other memory types, including Device, Normal non-cacheable, and Write-
through.
Any mix of memory types is possible, and each write can be a single write or a write burst.
Read issuing
capability
8n + 4m 8 for each core in the cluster including up to:
• 8 data linefills.
• 4 non-cacheable or Device data reads.
• 1 non-cacheable TLB page-walk read.
• 3 instruction linefills.
• 5 coherency operations.
• 8 DVM messages.
The 8 DVM messages per core can each be two-part DVM messages. They result in up to 16 DVM
transactions per core.
If an ACP is configured, up to 4 ACP linefill requests can be generated.
Exclusive thread
capability
n Each core can have 1 exclusive access sequence in progress.
Write ID
capability
16
The maximum number of outstanding write IDs is 16. This is the same as the maximum number of
outstanding writes.
Only Device memory types with nGnRnE or nGnRE can have more than one outstanding transaction with
the same AXI ID. All other memory types use a unique AXI ID for every outstanding transaction.
Write ID width 5 The ID encodes the source of the memory transaction. See Table A9-7 Encoding for AWIDM[4:0]
on page A9-121.
Read ID
capability
8n + 4m
8 for each core in the processor and 4 for the ACP.
Only Device memory types with nGnRnE or nGnRE can have more than one outstanding transaction with
the same AXI ID. All other memory types use a unique AXI ID for every outstanding transaction.
Two part DVMs use the same ID for both parts, and therefore can have two outstanding transactions on
the same ID.
Read ID width 6 The ID encodes the source of the memory transaction. See Table A9-8 Encoding for ARIDM[5:0]
on page A9-121.
In the following table, nn is the core number 0b00, 0b01, 0b10, or 0b11.
A9 ACE Master Interface
A9.5 Attributes of the ACE master interface
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
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