ARM Cortex-A35 User Manual

Table A9-5 ACE transactions and typical operations (continued)
Transaction Operation
Barriers DMB and DSB instructions. DVM sync snoops received from the interconnect.
WriteNoSnoop Non-cacheable store instructions. Evictions of non-shareable cache lines from L1 and L2.
WriteUnique Not used.
WriteLineUnique Not used.
WriteBack Evictions of dirty lines from the L1 or L2 cache, or streaming writes that are not allocating into the cache.
WriteClean Evictions of dirty lines from the L2 cache, when the line is still present in an L1 cache. Some cache
maintenance instructions.
WriteEvict Evictions of unique clean lines, when configured in the L2ACTLR.
Evict Evictions of clean lines, when configured in the L2ACTLR.
Related information
Arm® AMBA® AXI and ACE Protocol Specification AXI3, AXI4, and AXI4-Lite, ACE and ACE-Lite
A9 ACE Master Interface
A9.4 ACE transactions
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A9-119
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English