B1.118 TTBR1 with Long-descriptor translation table format
TTBR1 has a specific format when using the Long-descriptor translation table format. TTBCR.EAE
determines which format of the register is in use.
The following figure shows the TTBR1 bit assignments when TTBCR.EAE is 1.
BADDR[47:x]
4748 063
ASIDRES0
5556
Figure B1-66 TTBR1 bit assignments, TTBCR.EAE is 1
[63:56]
Reserved, RES0.
ASID, [55:48]
An ASID for the translation table base address. The TTBCR.A1 field selects either
TTBR0.ASID or TTBR1.ASID.
BADDR[47:x], [47:0]
Translation table base address, bits[47:x]. Bits [x-1:0] are RES0.
x is based on the value of TTBCR.T0SZ, and is calculated as follows:
• If TTBCR.T0SZ is 0 or 1, x = 5 - TTBCR.T0SZ.
• If TTBCR.T0SZ is greater than 1, x = 14 - TTBCR.T0SZ.
The value of x determines the required alignment of the translation table, that must be aligned to
2x bytes.
If bits [x-1:3] are not all zero, this is a misaligned Translation Table Base Address. Its effects are
CONSTRAINED UNPREDICTABLE, where bits [x-1:0] are treated as if all the bits are zero. The value
read back from those bits is the value written.
To access the 64-bit TTBR1 when TTBCR.EAE = 1:
MRRC p15, 1, <Rt>, <Rt2>, c2 ; Read 64-bit TTBR1 into Rt (low word) and Rt2 (high word)
MCRR p15, 1, <Rt>, <Rt2>, c2 ; Write Rt (low word) and Rt2 (high word) to 64-bit TTBR1
Register access is encoded as follows:
Table B1-97 TTBR0 access encoding
coproc opc1 CRm
1111 0001 0010
B1 AArch32 system registers
B1.118 TTBR1 with Long-descriptor translation table format
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-353
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