Inner region bits. Indicates the Inner Cacheability attributes for the memory associated with the
translation table walks. The possible values of IRGN[1:0] are:
0b00 Normal memory, Inner Non-cacheable.
0b01 Normal memory, Inner Write-Back Write-Allocate Cacheable.
0b10 Normal memory, Inner Write-Through Cacheable.
0b11 Normal memory, Inner Write-Back no Write-Allocate Cacheable.
The encoding of the IRGN bits is counter-intuitive, with register bit[6] being IRGN[0] and
register bit[0] being IRGN[1]. This encoding is chosen to give a consistent encoding of memory
region types and to ensure that software written for Armv7 without the Multiprocessing
Extensions can run unmodified on an implementation that includes the functionality introduced
by the Armv7 Multiprocessing Extensions.
To access the TTBR1 when TTBCR.EAE is 0:
MRC p15, 0, <Rt>, c2, c0, 1 ; Read TTBR1 into Rt
MCR p15, 0, <Rt>, c2, c0, 1 ; Write Rt to TTBR1
Register access is encoded as follows:
Table B1-96 TTBR1 access encoding
coproc opc1 CRn CRm opc2
1111 000 0010 0000 001
B1 AArch32 system registers
B1.117 TTBR1 with Short-descriptor translation table format
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-352
Non-Confidential
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